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? 2012-2013 microchip technology inc. ds20005155b-page 1 23a512/23lc512 device selection table features: spi-compatible bus interface: - 20 mhz clock rate - spi/sdi/sqi mode low-power cmos technology: - read current: 3 ma at 5.5v, 20 mhz - standby current: 4 ? a at +85c unlimited read and write cycles zero write time 64k x 8-bit organization: - 32-byte page byte, page and sequential mode for reads and writes high reliability temperature ranges supported: rohs compliant 8-lead soic, tssop and pdip packages pin function table description: the microchip technology inc. 23a512/23lc512 are 512kbit serial sram devices. the memory is accessed via a simple serial peripheral interface (spi) compatible serial bus. the bus signals required are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input. additionally, sdi (serial dual interface) and sqi (serial quad interface) is supported if your application needs faster data rates. this device also supports unlimited reads and writes to the memory array. the 23a512/23lc512 is available in standard packages including 8-lead soic, pdip and advanced 8-lead tssop. package types (not to scale) part number v cc range temp. ranges dual i/o (sdi) quad i/o (sqi) max. clock frequency packages 23a512 1.7-2.2v i, e yes yes 20 mhz (1) sn, st, p 23lc512 2.5-5.5v i, e yes yes 20 mhz (1) sn, st, p note 1: 16 mhz for e-temp. - industrial (i): -40 ? cto +85 ? c - automotive (e): -40 ? c to +125 ? c name function cs chip select input so/sio1 serial output/sdi/sqi pin sio2 sqi pin v ss ground si/sio0 serial input/sdi/sqi pin sck serial clock hold /sio3 hold/sqi pin v cc power supply cs so/sio1 sio2 v ss v cc hold /sio3 sck si/sio0 12 3 4 87 6 5 soic/tssop/pdip 512kbit spi serial sram wi th sdi and sqi interface downloaded from: http:///
23a512/23lc512 ds20005155b-page 2 ? 2012-2013 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.3v to v cc +0.3v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature under bias ................................................................................................. ............-40c to +125c table 1-1: dc characteristics ? notice : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating condit ions for an extended period of time may affect device reliability. dc characteristics industrial (i): t a = -40c to +85c automotive (e): t a = -40c to +125c param. no. sym. characteristic min. typ. max. units test conditions d001 v cc supply voltage 1.7 2.5 2 . 2 5.5 v 23a512 23lc512 d002 v ih high-level input voltage 0.7 v cc v cc + 0.3 v d003 v il low-level input voltage -0.3 0.2 v cc 0.1 v cc v 23a512 23lc512 d004 v ol low-level output voltage 0 . 2vi ol = 1 ma d005 v oh high-level output voltage v cc - 0.5 v i oh = -400 ? a d006 i li input leakage current 1 ? acs = v cc , v in = v ss or v cc d007 i lo output leakage current 1 ? acs = v cc , v out = v ss or v cc d008 i cc read operating current 13 1010 mama f clk = 20 mhz; so = o, 2.2v f clk = 20 mhz; so = o, 5.5v d009 i ccs standby current 1 4 4 1210 20 ? a ? a ? a ? a c s = v cc = 2.2v, inputs tied to v cc or v ss , i-temp cs = v cc = 2.2v, inputs tied to v cc or v ss , e-temp cs = v cc = 5.5v, inputs tied to v cc or v ss , i-temp cs = v cc = 5.5v, inputs tied to v cc or v ss , e-temp d010 c int input capacitance 7 pf v cc = 5.0v, f = 1 mhz, t a = 25c ( note 1 ) d011 v dr ram data retention voltage 1 . 0 v ( note 2 ) note 1: this parameter is periodically sampled and not 100% tested. 2: this is the limit to which v cc can be lowered without losing ram data. this parameter is periodically sampled and not 100% tested. 3: typical measurements taken at room temperature. downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 3 23a512/23lc512 table 1-3: ac test conditions table 1-2: ac characteristics ac characteristics industrial (i): t a = -40c to +85c automotive (e): t a = -40c to +125c param. no. sym. characteristic min. max. units test conditions 1f clk clock frequency 20 16 mhz i-temp e-temp 2t css cs setup time 25 32 n s i-temp e-temp 3t csh cs hold time 50 ns 4t csd cs disable time 25 32 n s i-temp e-temp 5 tsu data setup time 10 ns 6t hd data hold time 10 ns 7t r clk rise time 20 ns ( note 1 ) 8t f clk fall time 20 ns ( note 1 ) 9t hi clock high time 2532 n s i-temp e-temp 10 t lo clock low time 2532 n s i-temp e-temp 11 t cld clock delay time 2532 n s i-temp e-temp 12 t v output valid from clock low 2 5 32 ns i-temp e-temp 13 t ho output hold time 0 ns ( note 1 ) 14 t dis output disable time 2 0n s 15 t hs hold setup time 10 ns 16 t hh hold hold time 10 ns 17 t hz hold low to output high-z 10 ns 18 t hv hold high to output valid 50 ns note 1: this parameter is periodically sampled and not 100% tested. ac waveform: input pulse level 0.1 v cc to 0.9 v cc input rise/fall time 5 ns c l = 30 pf timing measurement reference level: input 0.5 v cc output 0.5 v cc downloaded from: http:///
23a512/23lc512 ds20005155b-page 4 ? 2012-2013 microchip technology inc. figure 1-1: hold timing figure 1-2: serial input timing (spi mode) figure 1-3: serial output timing (spi mode) cs sck so si hold 16 15 15 16 18 17 dont care 5 high-impedance n + 2 n + 1 n n - 1 n n + 2 n + 1 n n n - 1 cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 2 4 cs sck so 10 9 12 msb out lsb out 3 14 dont care si 13 downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 5 23a512/23lc512 2.0 functional description 2.1 principles of operation the 23a512/23lc512 is an 512kbit serial sram designed to interface directly with the serial peripheral interface (spi) port of many of todays popular microcontroller families, including microchips pic ? microcontrollers. it may also interface with microcon- trollers that do not have a built-in spi port by using discrete i/o lines programmed properly in firmware to match the spi protocol. in addition, the 23a512/ 23lc512 is also capable of operating in sdi/sqi high speed spi mode. the 23a512/23lc512 contains an 8-bit instruction reg- ister. the device is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low for the entire operation. table 2-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses and data are transferred msb first, lsb last. 2.2 modes of operation the 23x512 has three modes of operation that are selected by setting bits 7 and 6 in the mode register. the modes of operation are byte, page and burst. byte operation C is selected when bits 7 and 6 in the mode register are set to 00 . in this mode, the read/ write operations are limited to only one byte. the command followed by the 16-bit address is clocked into the device and the data to/from the device is transferred on the next eight clocks ( figure 2-1 , figure 2-2 ). page operation C is selected when bits 7 and 6 in the mode register are set to 10 . the 23x512 has 2048 pages of 32 bytes. in this mode, the read and write oper- ations are limited to within the addressed page (the address is automatically incremented internally). if the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page ( figure 2-3 , figure 2-4 ). sequential operation C is selected when bits 7 and 6 in the mode register are set to 01 . sequential opera- tion allows the entire array to be written to and read from. the internal address counter is automatically incremented and page boundaries are ignored. when the internal address counter reaches the end of the array, the address counter will roll over to 0x0000 ( figure 2-5 , figure 2-6 ). 2.3 read sequence the device is selected by pulling cs low. the 8-bit read instruction is transmitted to the 23a512/23lc512 followed by the 16-bit address. after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. if operating in sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached (ffffh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. the read operation is terminated by raising the cs pin. 2.4 write sequence prior to any attempt to write data to the 23a512/ 23lc512, the device must be selected by bringing cs low. once the device is selected, the write command can be started by issuing a write instruction, followed by the 16-bit address, and then the data to be written. a write is terminated by the cs being brought high. if operating in page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. the address pointer is automatically incremented. this operation can continue for the entire page (32 bytes) before data will start to be overwritten. if operating in sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the device. the internal address pointer is automati- cally incremented. when the address pointer reaches the highest address (ffffh), the address counter rolls over to (0000h). this allows the operation to continue indefinitely, however, previous data will be overwritten. downloaded from: http:///
23a512/23lc512 ds20005155b-page 6 ? 2012-2013 microchip technology inc. figure 2-1: byte read sequence (spi mode) figure 2-2: byte write sequence (spi mode) table 2-1: instruction set instruction name instruction format hex code description read 0000 0011 0x03 read data from memory array beginning at selected address write 0000 0010 0x02 write data to memory array beginning at selected address edio 0011 1011 0x3b enter dual i/o access eqio 0011 1000 0x38 enter quad i/o access rstio 1111 1111 0xff reset dual and quad i/o access rdmr 0000 0101 0x05 read mode register wrmr 0000 0001 0x01 write mode register so si sck cs 0 234567891011 21222324252627282930 31 1 01 0 0 0 0 01 15 14 13 12 210 76543210 instruction 16-bit address data out high-impedance so si cs 9 1011 21222324252627282930 31 00 0 0 0 0 01 15 14 13 12 210 76543210 instruction 16-bit address data byte high-impedance sck 0 234567 18 downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 7 23a512/23lc512 figure 2-3: page read sequence (spi mode) figure 2-4: page write sequence (spi mode) 76543210 page x, word y si cs 9 1011 21222324252627282930 31 15 14 13 12 210 16-bit address sck 0 234567 1 8 so cs 76543210 page x, word 0 sck 32 34 35 36 37 38 39 33 76543210 page x, word 31 76543210 page x, word y+1 page x, word y so high-impedance si 01 0 0 0 0 01 instruction si cs 9 1011 21222324252627282930 31 15 14 13 12 210 76543210 16-bit address sck 0 234567 18 cs si 76543210 page x, word 0 76543210 page x, word 31 76543210 page x, word y+1 page x, word y page x, word y sck 32 34 35 36 37 38 39 33 00 0 0 0 0 01 instruction downloaded from: http:///
23a512/23lc512 ds20005155b-page 8 ? 2012-2013 microchip technology inc. figure 2-5: sequential re ad sequence (spi mode) si cs 9 1011 21222324252627282930 31 15 14 13 12 210 76543210 instruction 16-bit address page x, word y sck 0 234567 18 so cs 76543210 page x+1, word 1 sck 76543210 page x+1, word 0 76543210 page x, word 31 so cs 76543210 page x+n, word 31 sck 76543210 page x+n, word 1 76543210 page x+1, word 31 so si si 01 0 0 0 0 01 downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 9 23a512/23lc512 figure 2-6: sequential write sequence (spi mode) si cs 9 1011 21222324252627282930 31 00 0 0 0 0 01 15 14 13 12 210 76543210 instruction 16-bit address data byte 1 sck 0 234567 18 si cs 41 42 43 46 47 76543210 data byte n sck 32 34 35 36 37 38 39 33 40 76543210 data byte 3 76543210 data byte 2 44 45 downloaded from: http:///
23a512/23lc512 ds20005155b-page 10 ? 2012-2013 microchip technology inc. 2.5 read mode register instruction ( rdmr ) the read mode register instruction ( rdmr ) provides access to the mode register. the mode register may be read at any time. the mode register is formatted as follows: table 2-2: mode register the mode bits indicate the operating mode of the sram. the possible modes of operation are: 0 0 = byte mode 1 0 = page mode 0 1 = sequential mode (default operation) 1 1 = reserved bits 0 through 5 are reserved and should always be set to 0 . see figure 2-7 for the rdmr timing sequence. figure 2-7: read mode regi ster timing sequence ( rdmr ) 76543210 w/r w/r C C C C C C mode mode 00000 0 w/r = writable/readable so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from mode register high-impedance sck 0 234567 1 8 3 downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 11 23a512/23lc512 2.6 write mode register instruction ( wrmr ) the write mode register instruction ( wrmr ) allows the user to write to the bits in the mode register as shown in table 2-2 . this allows for setting of the device operating mode. several of the bits in the mode register must be cleared to 0 . see figure 2-8 for the wrmr timing sequence. figure 2-8: write mode regi ster timing sequence ( wrmr ) 2.7 power-on state the 23a512/23lc512 powers on in the following state: the device is in low-power standby mode (cs = 1 ) a high-to-low-level transition on cs is required to enter active state so si cs 91011 12131415 01 0 0 0 0 00 7654 210 instruction data to mode register high-impedance sck 0 234567 18 3 downloaded from: http:///
23a512/23lc512 ds20005155b-page 12 ? 2012-2013 microchip technology inc. 3.0 pin descriptions the descriptions of the pins are listed in tab l e 3 - 1 . table 3-1: pin function table 3.1 chip select (cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. when the device is deselected, so goes to the high- impedance state, allowing multiple parts to share the same spi bus. after power-up, a low level on cs is required, prior to any sequence being initiated. 3.2 serial output (so) the so pin is used to transfer data out of the 23a512/ 23lc512. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 3.3 serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses, and data. data is latched on the rising edge of the serial clock. 3.4 serial dual interface pins(sio0, sio1) the sio0 and sio1 pins are used for sdi mode of operation. functionality of these i/o pins is shared with so and si. 3.5 serial quad interface pins (sio0 C sio3) the sio0 through sio3 pins are used for sqi mode of operation. because of the shared functionality of these pins the hold feature is not available when using sqi mode. 3.6 serial clock (sck) the sck is used to synchronize the communication between a master and the 23a512/23lc512. instruc- tions, addresses or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 3.7 hold function (hold ) the hold pin is used to suspend transmission to the 23a512/23lc512 while in the middle of a serial sequence without having to re-transmit the entire sequence over again. it must be held high any time this function is not being used. once the device is selected and a serial sequence is underway, the hold pin may be pulled low to pause further serial communication without resetting the serial sequence. the hold pin should be brought low while sck is low, otherwise the hold function will not be invoked until the next sck high-to-low transition. the 23a512/ 23lc512 must remain selected during this sequence. the si and sck levels are dont cares during the time the device is paused and any transitions on these pins will be ignored. to resume serial communication, hold should be brought high while the sck pin is low, otherwise serial communication will not be resumed until the next sck high-to-low transition. the so line will tri-state immediately upon a high-to low transition of the hold pin, and will begin outputting again immediately upon a subsequent low- to-high transition of the hold pin, independent of the state of sck. hold functionality is not available when operating in sqi mode. name soic/ pdip tssop function cs 1 chip select input so/sio1 2 serial data output/sdi/sqi pin sio2 3 sqi pin v ss 4g r o u n d si/sio0 5 serial data input/sdi/sqi pin sck 6 serial clock input hold /sio3 7 hold/sqi pin v cc 8 power supply downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 13 23a512/23lc512 3.8 spi/sdi and sqi pin designations cs sio1 nc vss vcc hold sck sio0 12 3 4 87 6 5 sdi mode: cs sio1 sio2 vss vcc sio3 sck sio0 12 3 4 87 6 5 sqi mode: cs sonc vss vcc hold scksi 12 3 4 87 6 5 spi mode: note: pin 3 should not be left floating when using spi/sdi mode. downloaded from: http:///
23a512/23lc512 ds20005155b-page 14 ? 2012-2013 microchip technology inc. 4.0 dual and quad serial mode the 23a512/23lc512 also supports sdi (serial dual) and sqi (serial quad) mode of operation when used with compatible master devices. as a convention for sdi mode of operation, two bits are entered per clock using the sio0 and sio1 pins. bits are clocked msb first. for sqi mode of operation, four bits of data are entered per clock, or one nibble per clock. the nibbles are clocked msb first. 4.1 dual interface mode the 23a512/23lc512 supports serial dual input (sdi) mode of operation. to enter sdi mode the edio com- mand must be clocked in ( figure 4-1 ). it should be noted that if the mcu resets before the sram, the user will need to determine the serial mode of operation of the sram and reset it accordingly. byte read and write sequence in sdi mode is shown in figure 4-2 and figure 4-3 . figure 4-1: enter sdi mode (edio) from spi mode 4.2 quad interface mode in addition to the serial dual interface (sdi) mode of operation serial quad interface (sqi) is also supported. in this mode the hold functionality is not available. to enter sqi mode the eqio command must be clocked in ( figure 4-4 ). sck 0 234567 1 si high-impedance so cs 00 0111 1 1 downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 15 23a512/23lc512 figure 4-2: byte read mode sdi figure 4-3: byte write mode sdi note: page and sequential mode are similar in that additional bytes can be clocked out before cs is brought high. note: the first byte read after the address will be a dummy byte. cs 91011 12 13 14 15 16 17 18 19 02 3 45 67 1 8 6420 14 12 10 8 7531 15 13 11 9 16-bit address instruction dummy byte 642 0 753 1 data out sck sio0 sio1 1 0 0 0 00 0 1 note: page and sequential mode are similar in that additional bytes can be clocked in before cs is brought high. cs 9101112 13 14 15 02 3 4 5 6 7 1 8 6420 14 12 10 8 7531 15 13 11 9 16-bit address instruction data in 642 0 753 1 sck sio1 0 0 0 0 00 0 1 sio0 downloaded from: http:///
23a512/23lc512 ds20005155b-page 16 ? 2012-2013 microchip technology inc. figure 4-4: enter sqi mode (eqio) from spi mode 4.3 exit sdi or sqi mode to exit from sdi mode, the rstio command must be issued. the command must be entered in the current device configuration, either sdi or sqi, see figure 4-7 and figure 4-8 . figure 4-5: byte read mode sqi sck 0 234567 1 si high-impedance so cs 0 0 0 111 0 0 note: page and sequential mode is similar in that additional bytes can be clocked out before cs is brought high. note: the first byte read after the address will be a dummy byte. cs sck 02 3 4 567 1 8 9 1 0 12 8 4 0 sio0 1 0 13 9 5 1 0 0 0 0 sio1 sio2 sio3 instruction 16-bit address dummy byte data out 14 10 6 2 15 11 7 3 73 6 2 5 1 4 0 downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 17 23a512/23lc512 figure 4-6: byte write mode sqi figure 4-7: reset sdi mode (rstio) C from sdi mode note: page and sequential mode are similar in that additional bytes can be clocked out before cs is brought high. cs sck 02 3 4 567 1 8 9 1 0 12 8 4 0 sio0 1 0 13 9 5 1 0 0 0 0 sio1 sio2 sio3 instruction 16-bit address data n data n+1 14 10 6 2 15 11 7 3 73 6 2 5 1 4 0 7 3 6 2 5 1 4 0 sck 0 2 3 1 sio0 cs 1111 sio1 11 1 1 downloaded from: http:///
23a512/23lc512 ds20005155b-page 18 ? 2012-2013 microchip technology inc. figure 4-8: reset sdi/sqi mode (rstio) C from sqi mode sck 0 1 sio0 cs 11 sio1 11 sio2 11 sio3 11 downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 19 23a512/23lc512 5.0 packaging information 5.1 package marking information 8-lead soic (3.90 mm) xxxxyyww xxxxxxxt nnn example: sn 1343 23a512i 1l7 legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec ? designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec ? designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 8-lead tssop example: xxxt yyww nnn 3lai 1343 1l7 t/xxxnnn xxxxxxxx yyww 8-lead pdip i/p 1l7 23a512 1343 example: 3 e part number 1st line marking codes pdip soic tssop 23a512 23a512 23a512 3aat 23lc512 23lc512 23lc512t 3lat note: t = temperature grade (i, e) downloaded from: http:///
23a512/23lc512 ds20005155b-page 20 ? 2012-2013 microchip technology inc. n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 21 23a512/23lc512 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
23a512/23lc512 ds20005155b-page 22 ? 2012-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 23 23a512/23lc512 downloaded from: http:///
23a512/23lc512 ds20005155b-page 24 ? 2012-2013 microchip technology inc. d n e e1 note 1 12 b e c a a1 a2 l1 l downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 25 23a512/23lc512 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
23a512/23lc512 ds20005155b-page 26 ? 2012-2013 microchip technology inc. appendix a: revision history revision a (september 2012) initial release. revision b (november 2013) added e-temp specs. downloaded from: http:///
? 2013 microchip technology inc. ds20005155b-page 27 23a512/23lc512 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
23a512/23lc512 ds20005155b-page 28 ? 2013 microchip technology inc. notes: downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 29 23a512/23lc512 product identification system to order or obtain information, e.g., on pr icing or delivery, refer to the factory or the listed sales office. not all possible ordering options are shown below. . part no. x /xx package tape & reel device device: 23a512 = 23lc512 = 512 kbit, 1.7 - 2.2v, spi serial sram 512 kbit, 2.5 - 5.5v, spi serial sram tape & reel: blank = t= standard packaging (tube) ta p e & r e e l temperature range: i=e= -40 ? c to +85 ? c -40 ? c to +125 ? c package: sn = st = p= plastic soic (3.90 mm body), 8-lead plastic tssop (4.4 mm body), 8-lead plastic pdip (300 mil body), 8-lead examples: a) 23a512-i/st = 512 kbit, 1.7-2.2v serial sram, industrial temp., tssop package b) 23lc512t-i/sn = 512 kbit, 2.5-5.5v serial sram, industrial temp., tape & reel, soic package c) 23lc512-i/p = 512 kbit, 2.5-5.5v serial sram, industrial temp., pdip package d) 23a512-e/st = 512 kbit, 1.7-2.2v serial sram, extended temp., tssop package e) 23lc512t-e/sn = 512 kbit, 2.5-5.5v serial sram, extended temp., tape & reel, soic package f) 23lc512-e/p = 512 kbit, 2.5-5.5v serial sram, extended temp., pdip package C x tem p range downloaded from: http:///
23a512/23lc512 ds20005155b-page 30 ? 2012-2013 microchip technology inc. notes: downloaded from: http:///
? 2012-2013 microchip technology inc. ds20005155b-page 31 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620776179 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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